MEMWAIT

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Interpret as MEMWAIT

MEMWAIT=0

Memory Wait Cycle Control Register

MEMWAIT	Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select thesystem clock source that is faster than 32 MHz (ICLK > 32 MHz). 0 (0): no wait 1 (1): wait
Reserved	These bits are read as 0000000. The write value should be 0000000.

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